This invention relates to the fields of duty cycle correction and differential pair circuits, and, more specifically, to methods of performing duty cycle correction, including but not limited to methods of performing duty cycle correction using differential pair circuits.
Many non-linear systems introduce into a sinusoidal signal non-linearities in the form of high frequency harmonics, each at an integer multiple of the fundamental frequency. The harmonics may be odd harmonics, i.e., harmonics the frequency of which is an odd integer multiple of the fundamental frequency, even harmonics, i.e, harmonics the frequency of which is an even integer multiple of the fundamental frequency, or both.
The introduction of even harmonics to sinusoidal signals is problematic in differential or balanced applications where it is desired to maintain odd symmetry. The reason is the non-uniform group delay, i.e., a delay which varies with frequency, typically exhibited by many transmission media delays higher frequency components of a signal more than the fundamental frequency. Because of this non-uniform group delay, transmission of the signal through the media delays the even harmonics in the sinusoidal signal more than the fundamental frequency, thus destroying the odd symmetry exhibited by the signal.
Consider, for example, a sinusoidal signal at a particular fundamental frequency. Such a signal exhibits odd symmetry only if it has a uniform (about 50%) duty cycle, i.e., a duty cycle in which the portion of the period T during which the signal is positive is about equal to the portion of the period T the signal is negative. If even harmonics are introduced into such a signal, and the signal then transmitted over a transmission media with a non-constant group delay, the duty cycle of the resultant signal will no longer be uniform, i.e., at about 50%. Consequently, the signal will no longer be suitable for differential or balanced applications where odd symmetry and a uniform duty cycle are required.
Consider, for example, the signal xy=1.2 sin(2xcfx80ty), identified with numeral 100 in FIG. 1. The signal zy=sin(2ty)+0.2 sin(4ty+xcfx80/2), identified in FIG. 1 with numeral 102, is representative of the signal xy to which has been added a second order harmonic with a phase shift of xcfx80/2. In addition, the signal zzy=sin(2xcfx80ty)+0.2 sin(4xcfx80ty+/4), identified in FIG. 1 with numeral 104, is representative of the signal xy to which has been added a second order harmonic with a phase shift of xcfx80/4. Both the signals zy and zzy are representative of the signals that might result from introducing even harmonics into the signal xy, and then passing the resultant signal through a transmission medium with a non-uniform group delay. While the signal xy has a 50% duty cycle, it will be observed that both the signals zy and zzy have non-uniform duty cycles, i.e., signals at other that a 50% duty cycle. This can be seen most readily by comparing the zero-crossing for the signal xy, identified with numeral 106, with that for the signals zy and zzy, identified with numeral 108, and observing that the latter zero crossings occur later in time that the former zero crossing, which occurs at ty=0.5.
As another example, consider again the signal xy=1.2 sin(2ty), identified with numeral 100 in FIG. 2. The signal zy=sin(2xcfx80ty)+0.2 sin(8xcfx80ty+xcfx80/2), identified in FIG. 2 with numeral 202, is representative of the signal xy to which has been added a fourth order harmonic with a phase shift of xcfx80/2. In addition, the signal zzy=sin(2xcfx80ty)+0.2 sin(8xcfx80ty+xcfx80/4), identified in FIG. 2 with numeral 204, is representative of the signal xy to which has been added a fourth order harmonic with a phase shift of xcfx80/4. Again, both the signals zy and zzy are representative of the signals that might result from introducing even harmonics into the signal xy, and then passing the resultant signal through a transmission medium with a non-uniform group delay. While the signal xy has a 50% duty cycle, it will be observed that both the signals zy and zzy have non-uniform duty cycles. This can be seen most readily by comparing the zero-crossing for the signal xy, identified with numeral 106, with that for the signals zy and zzy, identified with numeral 208, and observing that the latter zero crossings occur later in time that the former zero crossing, which occur at ty=0.5.
Other mechanisms exist for producing signals with non-uniform duty cycles when signals with uniform duty cycles are desired. Thus, what is needed is a method for performing duty cycle correction for signals having non-uniform duty cycles.
The invention provides a method of performing duty cycle correction of an input signal having a non-uniform duty cycle.
In this method, a signal is formed which is representative of the difference in duration between the positive and negative portions of the input signal duty cycle. A switching level is then derived from the signal. An output signal is formed through a switching action, whereby durations of positive and negative portions of the output signal duty cycle are defined by crossover points between the input signal and the switching level. The signal (and switching level) are then adjusted, if necessary, until the output signal duty cycle is substantially uniform.
In one embodiment, the signal representative of the difference in duration between the positive and negative portions of the input signal duty cycle is a DC voltage formed across one or more capacitors in a capacitor-degenerating differential pair circuit. A DC switching level is derived from the DC voltage. The output signal in this embodiment is formed through the switching actions of the differential pair circuit, whereby the durations of positive and negative portions of the output signal duty cycle are defined by crossover points between the input signal and the DC switching level. The DC voltage across the one or more capacitors (and the DC switching level) are automatically adjusted, if necessary, until the output signal duty cycle is at least substantially uniform.